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november 2006 rev 2 1/51 1 nand04ga3c2a nand04gw3c2a 4gbit, 2112 byte page, 3v, multi-level nand flash memory features high density multi-level cell (mlc) nand flash memories: ? up to 128 mbit spare area ? cost effective solutions for mass storage applications nand interface ? x8 bus width ? multiplexed address/ data supply voltages ?v dd = 2.7 to 3.6v core supply voltage for program, erase and read operations. ?v ddq = 1.7 to 1.95 or 2.7 to 3.6v for i/o buffers. page size: (2048 + 64 spare) bytes block size: (256k + 8k spare) bytes page read/program ? random access: 60s (max) ? sequential access: 60ns(min) ? page program operation time: 800s (typ) cache read mode ? internal cache register to improve the read throughput fast block erase ? block erase time: 1.5ms (typ) status register electronic signature serial number option chip enable ?don?t care? ? for simple interface with microcontroller data protection ? hardware program/erase locked during power transitions embedded error correction code (ecc) ? internal ecc accelerator ? easy ecc command interface data integrity ? 10,000 program/erase cycles (with ecc) ? 10 years data retention ecopack ? package available development tools ? bad blocks management and wear leveling algorithms ? file system os native reference software ? hardware simulation models tsop48 12 x 20mm table 1. product list reference part number density nand04gx3c2a nand04ga3c2a 4 gbits nand04gw3c2a www.st.com
nand04ga3c2a, nand04gw3c2a 2/51 contents 1 summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1 bad blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 inputs/outputs (i/o0-i/o7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 address latch enable (al) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.3 command latch enable (cl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.4 chip enable (e) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.5 read enable (r) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.6 write enable (w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.7 write protect (wp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.8 ready/busy (rb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.9 v dd supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.10 v ss ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.11 vssq . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.12 vddq . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.1 command input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.2 address input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.3 data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.4 data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.5 write protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.6 standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5 command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 device operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.1 read memory array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.2 random read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
nand04ga3c2a, nand04gw3c2a 3/51 6.3 page read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.4 cache read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.5 page program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.6 sequential input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.7 random data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.8 block erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.9 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.10 read status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.10.1 write protection bit (sr7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.10.2 p/e/r controller and cache ready/busy bit (sr6) . . . . . . . . . . . . . . . 25 6.10.3 p/e/r controller bit (sr5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.10.4 error bit (sr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.10.5 sr4, sr3, sr2 and sr1 are reserved . . . . . . . . . . . . . . . . . . . . . . . . 25 6.11 read electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7 data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8 embedded ecc accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9 software algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9.1 bad block management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9.2 block replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9.3 garbage collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9.4 wear-leveling algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9.5 hardware simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 9.5.1 behavioral simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 9.5.2 ibis simulations models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 10 program and erase times and endurance cycles . . . . . . . . . . . . . . . . . 33 11 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 12 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 12.1 ready/busy signal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . 46 13 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
nand04ga3c2a, nand04gw3c2a 4/51 14 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 15 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
nand04ga3c2a, nand04gw3c2a 5/51 list of tables table 1. product list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. product description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 4. valid blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 5. bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 6. address insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 7. address definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 8. commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 9. status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 10. electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 11. electronic signature byte 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 12. electronic signature byte 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 13. block failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 14. program, erase times and program erase endurance cycles . . . . . . . . . . . . . . . . . . . . . 33 table 15. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 16. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 17. capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 18. dc characteristics, vddq 3v devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 19. ac characteristics for command, address, data input, vddq 3v devices . . . . . . . . . . . 37 table 20. ac characteristics for operations, vddq 3v devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 21. tsop48 - 48 lead plastic thin small outline, 12 x 20 mm, package mechanical data. . . 48 table 22. ordering information scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 23. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
nand04ga3c2a, nand04gw3c2a 6/51 list of figures figure 1. logic block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 2. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 3. tsop48 connections x8 devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0 figure 4. memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 5. read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 6. random data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 7. cache read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 8. page program operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 9. random data input during sequential data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 10. block erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 11. bad block management flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 0 figure 12. garbage collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 13. command latch ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 14. address latch ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 15. data input latch ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 16. sequential data output after read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 17. read status register ac waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 18. read electronic signature ac waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 19. page read operation ac waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 20. page program ac waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 21. block erase ac waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 22. reset ac waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 23. program/erase enable waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 figure 24. program/erase disable waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 figure 25. ready/busy ac waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 26. ready/busy load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 27. resistor value versus waveform timings for ready/busy signal . . . . . . . . . . . . . . . . . . 47 figure 28. tsop48 - 48 lead plastic thin small outline, 12 x 20 mm, package outline . . . . . . . . . . 48
nand04ga3c2a, nand04gw3c 2a 1 summary description 7/51 1 summary description the nand04ga3c2a and nand04gw3c2a are a multi-level cell(mlc) devices from the nand flash 2112 byte page family of non-vol atile flash memories. the devices are offered in 1.8v and 3v v ddq i/o power supplies. the core voltage is 3v v dd. the size of a page is 2112 bytes (2048 + 64 spare). the address lines are multiplexed with the data input/output signals on a multiplexed x8 input/output bus. this interface reduces the pin count and makes it possible to migrate to other densities without changing the footprint. each block can be programmed and erased over 10,000 cycles. the devices also have hardware security features; a write protect pin is available to give hardware protection against program and erase operations. the devices feature an open-drain ready/busy output that can be used to identify if the program/erase/read (p/e/r) controller is currently active. the use of an open-drain output allows the ready/busy pins from several memories to be connected to a single pull-up resistor. each device has a cache read feature which improves the read throughput for large files. during cache reading, the device loads the da ta in a cache register while the previous data is transferred to the i/o buffers to be read. all devices have the chip enable don?t care feature, which allows code to be directly downloaded by a microcontroller, as chip enable transitions during the latency time do not stop the read operation there is the option of a unique identifier (serial number), which allows each device to be uniquely identified. it is subject to an nda (non disclosure agreement) and is therefore not described in the datasheet. for more details of this option contact your nearest st sales office. the nand04ga3c2a and nand04gw3c2a are available in a tsop48 (12 x 20mm) package. in order to meet environmental requirements, st offers the devices in ecopack ? packages. ecopack packages are lead-free. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com. for information on how to order these options refer to table 22: ordering information scheme . devices are shipped from the factory with block 0 always valid and the memory content bits, in valid blocks, erased to ?1?. see table 2: product description , for all the devices available in the family. table 2. product description reference part number density bus width page size block size memory array operating voltage v dd operating vo lt ag e v ddq timings package random access (max) sequential access (min) page program (typ) block erase (typ) nand04gx3c2a nand04gw3c2a 4gbits x8 2048+ 64 bytes 256k+ 8k bytes 128 pages x 2048 blocks 2.7 to 3.6v 2.7v to 3.6v 60s 60ns 800s 1.5ms tsop48 nand04ga3c2a 2.7 to 3.6v 1.7v to 1.95v
1 summary description nan d04ga3c2a, nand04gw3c2a 8/51 figure 1. logic block diagram address register/counter command interface logic p/e/r controller high voltage generator wp buffers e w ai11009b r y decoder page buffer nand flash memory array x decoder command register cl al cache register rb data register i/o
nand04ga3c2a, nand04gw3c 2a 1 summary description 9/51 figure 2. logic diagram table 3. signal names i/o0 - i/o7 data input / outputs cl command latch enable al address latch enable e chip enable r read enable w write enable wp write protect rb ready / busy (open drain output) v dd power supply v ddq i/o power v ss ground v ssq i/o ground nc no connection du do not use ai12702b w i/o0 - i/o7 x8 v dd nand04ga3c2a nand04gw3c2a e v ss wp al cl rb r v ddq v ssq
1 summary description nan d04ga3c2a, nand04gw3c2a 10/51 figure 3. tsop48 connections x8 devices i/o3 i/o2 i/o6 r rb nc i/o4 i/o7 ai12703b nand04ga3c2a nand04gw3c2a 12 1 13 24 25 36 37 48 e i/o1 nc nc nc nc nc nc nc wp w nc nc nc v ss v dd al nc nc cl nc i/o5 nc nc nc i/o0 nc nc nc nc v ddq nc nc nc v ssq nc nc nc nc nc
nand04ga3c2a, nand04gw3c2a 2 memory array organization 11/51 2 memory array organization the memory array is made up of nand structures where 32 cells are connected in series. the memory array is organized in blocks where each block contains 128 pages. the array is split into two areas, the main area and the spare area. the main area of the array is used to store data whereas the spare area is typically used to store software flags or bad block identification. the pages are split into a 2048 byte main area and a spare area of 64 bytes.refer to figure 4: memory array organization . 2.1 bad blocks the nand04ga3c2a and nand04gw3c2a devi ces may contain bad blocks, that is blocks that contain one or more invalid bits whose reliability is not guaranteed. additional bad blocks may develop during the lifetime of the device. the bad block information is written prior to shipping (refer to section 9.1: bad block management for more details). table 4: valid blocks shows the minimum number of valid blocks in each device. the values shown include both the bad blocks that are present when the device is shipped and the bad blocks that could develop later on. these blocks need to be managed using bad blocks management and block replacement (refer to section 9: software algorithms ). table 4. valid blocks density of device min max 4 gbits 2008 2048
2 memory array organization nand04ga3c2a, nand04gw3c2a 12/51 figure 4. memory array organization ai12704 block = 128 pages page = 2112 bytes (2,048 + 64) 2,048 bytes 2048 bytes spare area 64 bytes block 8 bits 64 bytes 8 bits page page buffer, 2112 bytes main area
nand04ga3c2a, nand04gw3c 2a 3 signal descriptions 13/51 3 signal descriptions see figure 1: logic block diagram , and table 3: signal names , for a brief overview of the signals connected to this device. 3.1 inputs/outputs (i/o0-i/o7) input/outputs 0 to 7 are used to input the selected address, output the data during a read operation or input a command or data during a write operation. the inputs are latched on the rising edge of write enable. i/o0-i/o7 are left floating when the device is deselected or the outputs are disabled. 3.2 address latch enable (al) the address latch enable activates the latching of the address inputs in the command interface. when al is high, the inputs are latched on the rising edge of write enable. 3.3 command latch enable (cl) the command latch enable activates the latching of the command inputs in the command interface. when cl is high, the inputs are latched on the rising edge of write enable. 3.4 chip enable (e ) the chip enable input activates the memory control logic, input buffers, decoders and sense amplifiers. when chip enable is low, v il , the device is selected. if chip enable goes high, v ih , while the device is busy, the device remains selected and does not go into standby mode. 3.5 read enable (r ) the read enable pin, r , controls the sequential data output during read operations. data is valid t rlqv after the falling edge of r . the falling edge of r also increments the internal column address co unter by one. 3.6 write enable (w ) the write enable input, w , controls writing to the command interface, input address and data latches. both addresses and data are latched on the rising edge of write enable. during power-up and power-down a recovery time of 10s (min) is required before the command interface is ready to accept a command. it is recommended to keep write enable high during the recovery time.
3 signal descriptions nand0 4ga3c2a, nand04gw3c2a 14/51 3.7 write protect (wp ) the write protect pin is an input that gives a hardware protection against unwanted program or erase operations. when write protect is low, v il , the device does not accept any program or erase operations. it is recommended to keep the write protect pin low, v il , during power-up and power-down. 3.8 ready/busy (rb ) the ready/busy output, rb , is an open-drain output that can be used to identify if the p/e/r controller is currently active. when ready/busy is low, v ol , a read, program or erase operation is in progress. when the operation completes ready/busy goes high, v oh . the use of an open-drain output allows the ready/busy pins from several memories to be connected to a single pull-up resistor. a low will then indicate that one, or more, of the memories is busy. refer to the section 12.1: ready/busy signal electrical characteristics for details on how to calculate the value of the pull-up resistor. 3.9 v dd supply voltage v dd provides the power supply to the internal core of the memory device. it is the main power supply for operations (read, program and erase). 3.10 v ss ground ground, v ss, is the reference for the power supply. it must be connected to the system ground. 3.11 v ssq v ssq is the ground reference for the i/o power supply. it must be connected to the system ground. 3.12 v ddq v ddq provides power to the i/o buffers.
nand04ga3c2a, nand04gw 3c2a 4 bus operations 15/51 4 bus operations there are six standard bus operations that control the memory. each of these is described in this section, see table 5: bus operations , for a summary. typically, glitches of less than 5 ns on ch ip enable, write enable and read enable are ignored by the memory and do not affect bus operations. 4.1 command input command input bus operations are used to give commands to the memory. commands are accepted when chip enable is low, command latch enable is high, address latch enable is low and read enable is high. they are latched on the rising edge of the write enable signal. only i/o0 to i/o7 are used to input commands. see figure 13 and ta b l e 1 9 for details of the timings requirements. 4.2 address input address input bus operations are used to input the memory addresses. five bus cycles are required to input the addresses (refer to table 6: address insertion ). the addresses are accepted when chip enable is low, address latch enable is high, command latch enable is low and read enable is high. they are latched on the rising edge of the write enable signal. only i/o0 to i/o7 are used to input addresses. see figure 14 and ta b l e 1 9 for details of the timings requirements. 4.3 data input data input bus operations are used to input the data to be programmed. data is only accepted when chip enable is low, address latch enable is low, command latch enable is low and read enable is high. the data is latched on the rising edge of the write enable signal. the data is input sequentially using the write enable signal. see figure 15 and ta b l e 1 9 for details of the timing requirements. 4.4 data output data output bus operations are used to read: the data in the memory array, the status register, the electronic signature and the unique identifier. data is output when chip enable is low, writ e enable is high, address latch enable is low, and command latch enable is low. the data is output sequentially using the read enable signal. see figure 16 and ta b l e 2 0 for details of the timings requirements.
4 bus operations nand04ga3c2a, nand04gw3c2a 16/51 4.5 write protect write protect bus operations are used to pr otect the memory against program or erase operations. when the write protect signal is low the device will not accept program or erase operations and so the contents of the memory array cannot be altered. the write protect signal is not latched by write enable to ensure protection even during power-up. 4.6 standby the memory enters standby mode by driving chip enable, e , high. in standby mode, the device is deselected, outputs are disabled and power consumption is reduced. table 5. bus operations bus operation e al cl r w wp i/o0 - i/o7 command input v il v il v ih v ih rising x (1) command address input v il v ih v il v ih rising x address data input v il v il v il v ih rising v ih data input data output v il v il v il falling v ih x data output write protect x x x x x v il x standby v ih xxx xv il /v dd x 1. wp must be v ih when issuing a program or erase command. table 6. address insertion (1) bus cycle i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 1 st a7 a6 a5 a4 a3 a2 a1 a0 2 nd v il v il v il v il a11 a10 a9 a8 3 rd a19 a18 a17 a16 a15 a14 a13 a12 4 th a27 a26 a25 a24 a23 a22 a21 a20 5 th v il v il v il v il v il v il a29 a28 1. any additional address input cycles will be ignored. table 7. address definitions address definition a0 - a11 column address a12 - a18 page address a19 - a29 block address
nand04ga3c2a, nand04gw3c2a 5 command set 17/51 5 command set all bus write operations to the device are interpreted by the command interface. the commands are input on i/o0-i/o7 and are latched on the rising edge of write enable when the command latch enable signal is high. device operations are selected by writing specific commands to the command register. the two-step command sequences for program and erase operations are imposed to maximize data security. the commands are summarized in table 8: commands . table 8. commands command bus write operations (1) commands accepted during busy 1 st cycle 2 nd cycle 3 rd cycle 4 th cycle read 00h (2) 30h ? ? random data output 05h e0h ? ? cache read 00h 31h ? ? exit cache read 34h ? ? ? ye s (3) page program (sequential input default) 80h 10h ? ? random data input 85h ? ? ? block erase 60h d0h ? ? reset ffh ? ? ? ye s read electronic signature 90h ? ? ? read status register 70h ? ? ? ye s 1. the bus cycles are only shown for issu ing the codes. the cycles required to i nput the addresses or input/output data are not shown. 2. for consecutive read operations the 00h command does not need to be repeated. 3. only when a cache read operation is ongoing.
6 device operations nand0 4ga3c2a, nand04gw3c2a 18/51 6 device operations the following section gives the details of the device operations. 6.1 read memory array at power-up the device defaults to read mode. to enter read mode from another mode the read command must be issued, see table 8: commands . once a read command is issued, subsequent consecutive read commands only require the confirm command code (30h). once a read command is issued two types of operations are available: random read and page read. 6.2 random read each time the read command is issued the first read is random read. 6.3 page read after the first random read access, the page data (2112 bytes) is transferred to the page buffer in a time of t whbh (refer to ta b l e 2 0 for value). once the transfer is complete the ready/busy signal goes high. the data can then be read out sequentially (from selected column address to last column address) by pulsing the read enable signal. the device can output random data in a page, instead of the consecutive sequential data, by issuing a random data output command . the random data output command can be used to skip some data during a sequential data output. the sequential operation can be resumed by changing the column address of the next data to be output, to the address which follows the random data output command. the random data output command can be issued as many times as required within a page. the random data output command is not accepted during cache read operations.
nand04ga3c2a, nand04gw3c2a 6 device operations 19/51 figure 5. read operations 1. highest address depends on device density. cl e w al r i/o rb 00h ai11016 busy command code data output (sequentially) address input tblbh1 30h command code
6 device operations nand0 4ga3c2a, nand04gw3c2a 20/51 figure 6. random data output 6.4 cache read the cache read operation is used to improve the read throughput by reading data using the cache register. as soon as the user starts to read one page, the device automatically loads the next page into the cache register. an cache read operation consists of three steps (see ta b l e 8 ): 1. one bus cycle is required to setup the cache read command (the same as the standard read command). 2. five bus cycles are then required to input the start address (refer to ta b l e 6 ). 3. one bus cycle is required to issue the cache read confirm command to start the p/e/r controller. the start address must be at the beginning of a page (column address = 000h, see ta b l e 7. ). this allows the data to be output uninterrupted after the latency time (t blbh1 ), see figure 7. i/o rb address inputs ai08658b data output busy tblbh1 (read busy time) 000h cmd code 30h address inputs data output 05h e0h 5 add cycles main area spare area col add 1,2 row add 1,2,3 cmd code cmd code cmd code 2add cycles main area spare area col add 1,2 r
nand04ga3c2a, nand04gw3c2a 6 device operations 21/51 the ready/busy signal can be used to monitor the start of the operation. during the latency period the ready/busy signal goes low, after this the ready/busy signal goes high, even if the device is internally downloading page n+1. once the cache read operation has started, the status register can be read using the read status register command. during the operation, sr5 can be read, to find out whether the internal reading is ongoing (sr5 = ?0?), or has completed (sr5 = ?1?), wh ile sr6 indicates whether the cache register is ready to download new data. to exit the cache read operation an exit cache read command must be issued (see ta bl e 8 ). figure 7. cache read operation 6.5 page program the page program operation is the standard operation to program data to the memory array. generally, data is programmed sequentially, however the device does support random input within a page. the memory array is programmed by page, however partial page programming is allowed where any number of bytes (1 to 2112) can be programmed. only one consecutive partial page program operations is allowed on the same page. after exceeding this a block erase command must be issued before any further program operations can take place in that page. i/o rb address inputs ai08661 00h read setup code 31h cache read confirm code busy tblbh1 (read busy time) 1st page data output 2nd page 3rd page last page 34h exit cache read code block n
6 device operations nand0 4ga3c2a, nand04gw3c2a 22/51 6.6 sequential input to input data sequentially the addresses must be sequential and remain in one block. for sequential input each page program operation comprises five steps: 1. one bus cycle is required to setup the page program (sequential input) command (see ta bl e 8 ). 2. five bus cycles are then required to input the program address (refer to ta bl e 6 ). 3. the data is then loaded into the data registers. 4. one bus cycle is required to issue the page program confirm command to start the p/e/r controller. the p/e/r will only start if the data has been loaded in step 3. 5. the p/e/r controller then programs the data into the array. 6.7 random data input during a sequential input operation, the next sequential address to be programmed can be replaced by a random address, by issuing a random data input command. the following two steps are required to issue the command: 1. one bus cycle is required to setup the random data input command (see ta b l e 8 ). 2. two bus cycles are then required to input the new column address (refer to ta bl e 6 ). random data input can be repeated as often as required in any given page. once the program operation has started the status register can be read using the read status register command. during program ope rations the status register will only flag errors for bits set to '1' that have not been successfully programmed to '0'. during the program operation, only the read status register and reset commands will be accepted, all other comm ands will be ignored. once the program operation has completed the p/ e/r controller bit sr6 is set to ?1? and the ready/busy signal goes high. the device remains in read status register mode until another valid command is written to the command interface. figure 8. page program operation i/o rb address inputs sr0 ai08659 data input 10h 70h 80h page program setup code confirm code read status register busy tblbh2 (program busy time)
nand04ga3c2a, nand04gw3c2a 6 device operations 23/51 figure 9. random data input during sequential data input 6.8 block erase erase operations are done one block at a time. an erase operation sets all of the bits in the addressed block to ?1?. all previous data in the block is lost. an erase operation consists of three steps (refer to figure 10 : 1. one bus cycle is required to setup the block erase command. only addresses a19 to a30 are used, the other address inputs are ignored. 2. three bus cycles are then required to load the address of the block to be erased. refer to ta bl e 7 for the block addresses of each device. 3. one bus cycle is required to issue the block erase confirm command to start the p/e/r controller. the operation is initiated on the rising edge of write enable, w , after the confirm command is issued. the p/e/r controller handles block erase and implements the verify process. during the block erase operation, only the read status register and reset commands will be accepted, all other commands will be ignored. once the program operation has completed the p/ e/r controller bit sr6 is set to ?1? and the ready/busy signal goes high. if the operation completed successfully, the write status bit sr0 is ?0?, otherwise it is set to ?1?. i/o address inputs ai08664 data intput 80h cmd code address inputs data input 85h 5 add cycles main area spare area col add 1,2 row add 1,2,3 cmd code 2 add cycles main area spare area col add 1,2 rb busy tblbh2 (program busy time) sr0 10h 70h confirm code read status register
6 device operations nand0 4ga3c2a, nand04gw3c2a 24/51 figure 10. block erase operation 6.9 reset the reset command is used to reset the command interface and status register. if the reset command is issued during any operation, the operati on will be aborted. if it was a program or erase operation that was aborted, the contents of the memory locations being modified will no longer be valid as the data will be pa rtially programmed or erased. if the device has already been reset then the new reset command will not be accepted. the ready/busy signal goes low for t whbh1 after the reset command is issued. the value of t whbh1 depends on the operation that the device was performing when the command was issued, refer to ta b l e 2 0 for the values. 6.10 read status register the device contains a status register which provides information on the current or previous program or erase operation. the various bits in the status register convey information and errors on the operation. the status register is read by issuing the read status register command. the status register information is present on the output data bus (i/o0-i/ o7) on the falling edge of chip enable or read enable, whichever occurs last. when several memories are connected in a system, the use of chip enable and read enab le signals allows the system to poll each device separately, even when the ready/busy pins are common-wired. it is not necessary to toggle the chip enable or read enable signals to update the contents of the status register. after the read status register command has been issued, the device remains in read status register mode until another command is issued. therefore if a read status register command is issued during a random read cycle a new read command must be issued to continue with a page read operation. refer to ta b l e 9 where status register bits are summarized. it should also be read in conjunction with the following text descriptions. 6.10.1 write protection bit (sr7) the write protection bit can be used to identify if the device is protected or not. if the write protection bit is set to ?1? the device is not protected and program or erase operations are allowed. if the write protection bit is set to ?0? the device is protected and program or erase operations are not allowed. i/o rb block address inputs sr0 ai07593 d0h 70h 60h block erase setup code confirm code read status register busy tblbh3 (erase busy time)
nand04ga3c2a, nand04gw3c2a 6 device operations 25/51 6.10.2 p/e/r controller and cache ready/busy bit (sr6) status register bit sr6 has two different functions depending on the current operation. during cache read operations sr6 acts as a cache ready/busy bit, which indicates whether the cache register is ready to accept new data. when sr6 is set to '0', the cache register is busy and when sr6 is set to '1', the cache register is ready to accept new data. during all other operations sr6 acts as a p/e/r controller bit, which indicates whether the p/e/r controller is active or inactive. when th e p/e/r controller bit is set to ?0?, the p/e/r controller is active (device is bu sy); when the bit is set to ?1?, the p/e/r controller is inactive (device is ready). 6.10.3 p/e/r controller bit (sr5) the program/erase/read controller bit indicates whether the p/e/r controller is active or inactive. when the p/e/r controller bit is set to ?0?, the p/e/r controlle r is active; when the bit is set to ?1?, the p/ e/r controller is inactive. 6.10.4 error bit (sr0) the error bit is used to identify if any errors have been detected by the p/e/r controller. the error bit is set to ?1? when a program or erase operation has failed to write the correct data to the memory. if the error bit is set to ?0? the operation has completed successfully. 6.10.5 sr4, sr3, sr2 and sr1 are reserved
6 device operations nand0 4ga3c2a, nand04gw3c2a 26/51 6.11 read electronic signature the device contains a manufacturer code and device code. to read these codes three steps are required: 1. one bus write cycle to issue the read electronic signature command (90h) 2. one bus write cycle to input the address (00h) 3. four bus read cycles to sequentially output the data (as shown in table 10: electronic signature ). table 9. status register bits bit name logic level definition sr7 write protection '1' not protected '0' protected sr6 (1) program/ erase/ read controller '1' p/e/r c inactive, device ready '0' p/e/r c active, device busy cache ready/busy '1' cache register ready (cache read only) '0' cache register busy (cache read only) sr5 program/ erase/ read controller (2) '1' p/e/r c inactive '0' p/e/r c active sr4, sr3, sr2, sr1 reserved don?t care sr0 (1) generic error ?1? error ? operation failed ?0? no error ? operation successful 1. the sr6 bit and sr0 bit have a differe nt meaning during cache read operations. 2. only valid for cache read operations, fo r other operations it is same as sr6. table 10. electronic signature part number byte/word 1 byte/word 2 byte 3 (see table 11 ) byte 4 (see table 12 ) manufacturer code device code nand04ga3c2a 20h dch 84h 25h nand04gw3c2a 20h dch 84h
nand04ga3c2a, nand04gw3c2a 6 device operations 27/51 table 11. electronic signature byte 3 i/o definition value description i/o1-i/o0 internal chip number 0 0 0 1 1 0 1 1 1 2 4 8 i/o3-i/o2 cell type 0 0 0 1 1 0 1 1 2-level cell 4-level cell 8-level cell 16-level cell i/o5-i/o4 number of simultaneously programmed pages 0 0 0 1 1 0 1 1 1 2 4 8 i/o7-i/o6 reserved 10 table 12. electronic signature byte 4 i/o definition value description i/o1-i/o0 page size (without spare area) 0 0 0 1 1 0 1 1 1 kbytes 2 kbytes reserved reserved i/o2 spare area size (byte / 512 byte) 0 1 8 16 i/o7, i/o3 minimum sequential access time 0 0 1 0 0 1 1 1 50ns 30ns reserved reserved i/o5-i/o4 block size (without spare area) 0 0 0 1 1 0 1 1 64 kbytes 128 kbytes 256 kbytes reserved i/o6 organization 0 1 x8 x16
7 data protection nand04ga3c2a, nand04gw3c2a 28/51 7 data protection the device has hardware features to protect against program and erase operations. it features a write protect, wp , pin, which can be used to protect the device against program and erase operations. it is recommended to keep wp at v il during power-up and power- down. 8 embedded ecc accelerator the nand04ga3c2a and nand04gw3c2a devi ces include a powerful embedded error correction code (ecc) accelerator. this feat ure ensures high memory reliability and fast data throughput while simplifying the design of the memory application. if the embedded ecc accelerator cannot be used, it is strongly recommended to use an external hardware accelerator to maintain the same data throughput. if this proves to be impossible, a software ecc can be implemented. however, this solution will result in lower performance compared to the hardware ecc solution. the ecc operation and command set are described in a dedicated application note. please contact the nearest stmicroelectronics sales office for further details.
nand04ga3c2a, nand04gw3c 2a 9 software algorithms 29/51 9 software algorithms this section gives information on the software algorithms that st recommends to implement to manage the bad blocks and extend the lifetime of the nand device. nand flash memories are programmed and erased by fowler-nordheim tunneling using a high voltage. exposing the device to a high voltage for extended periods can cause the oxide layer to be damaged. for this reason, the number of program and erase cycles is limited (see ta b l e 1 4 for value) and it is recommended to implement garbage collection, wear-leveling and error correction code algorithms to extend the number of program and erase cycles and increase the data retention. to help integrate a nand memory into an applic ation st microelectronics can provide a file system os native reference software, whic h supports the basic commands of file management. contact the nearest st microelectronics sales office for more details. 9.1 bad block management devices with bad blocks have the same quality level and the same ac and dc characteristics as devices where all the blocks are valid. a bad block does not affect the performance of valid blocks because it is isolated from the bit line and common source line by a select transistor. the devices are supplied with all the locations inside valid blocks erased (ffh). the bad block information is written prior to shipping. any block, where the 1st byte in the spare area of the last page, does not contain ffh, is a bad block. the bad block information must be read before any erase is attempted as the bad block information may be erased. for the system to be able to recognize the bad blocks based on the original information it is recommended to create a bad block table following the flowchart shown in figure 11. 9.2 block replacement over the lifetime of the device additional bad blocks may develop. in this case the block has to be replaced by copying the data to a valid block. these additional bad blocks can be identified as attempts to program or erase t hem will give errors in the status register. as the failure of a page program operation does not affect the data in other pages in the same block, the block can be replaced by re-programming the current data and copying the rest of the replaced block to an available valid block. refer to ta b l e 1 3 for the recommended procedure to follow if an error occurs during an operation.
9 software algorithms nan d04ga3c2a, nand04gw3c2a 30/51 figure 11. bad block management flowchart figure 12. garbage collection table 13. block failure operation recommended procedure erase block replacement program block replacement or ecc (1) read ecc (1) 1. example: 4 bit correction per 528 bytes. ai07588c start end no yes yes no block address = block 0 data = ffh? last block? increment block address update bad block table valid page invalid page free page (erased) old area ai07599b new area (after gc)
nand04ga3c2a, nand04gw3c 2a 9 software algorithms 31/51 9.3 garbage collection when a data page needs to be modified, it is faster to write to the first available page, and the previous page is marked as invalid. after several updates it is necessary to remove invalid pages to free some memory space. to free this memory space and allow further program operations it is recommended to implement a garbage collection algorithm. in a garbage collection software the valid pages are copied into a free area and the block containing the invalid pages is erased (see figure 12 ). 9.4 wear-leveling algorithm for write-intensive applications, it is recommended to implement a wear-leveling algorithm to monitor and spread the number of write cycles per block. in memories that do not use a wear-leveling algorithm not all blocks get used at the same rate. blocks with long-lived data do not endure as many write cycles as the blocks with frequently-changed data. the wear-leveling algorithm ensures that equal use is made of all the available write cycles for each block. there are two wear-leveling levels: 1. first level wear-leveling, new data is programmed to the free blocks that have had the fewest write cycles 2. second level wear-leveling, long-lived data is copied to another block so that the original block can be used for more frequently-changed data. the second level wear-leveling is triggered when the difference between the maximum and the minimum number of write cycles per block reaches a specific threshold.
9 software algorithms nan d04ga3c2a, nand04gw3c2a 32/51 9.5 hardware simulation models 9.5.1 behavioral simulation models denali software corporation models are platform independent functional models designed to assist customers in perfor ming entire system simulations (typical vhdl/verilog). these models describe the logic behavior and timings of nand flash devices, and so allow software to be developed before hardware. 9.5.2 ibis simulations models ibis (i/o buffer information specification) models describe the behavior of the i/o buffers and electrical characteristics of flash devices. these models provide information such as ac characteristics, rise/fall times and package mechanical data, all of which are measured or simulated at voltage and temperature ranges wider than those allowed by target specifications. ibis models are used to simu late pcb connections and can be used to resolve compatibility issues when upgrading devices. they can be imported into spicetools.
nand04ga3c2a, nand04gw3c2a 10 program and erase times and endurance cycles 33/51 10 program and erase times and endurance cycles the program and erase times and the number of program/ erase cycles per block are shown in ta b l e 1 4 table 14. program, erase times and program erase endurance cycles parameters nand04ga3c2a, nand04gw3c2a unit min typ max page program time 800 2000 s block erase time 1.5 3ms program/erase cycles (per block) 10,000 cycles data retention 10 years
11 maximum rating nand04ga3c2a, nand04gw3c2a 34/51 11 maximum rating stressing the device above the ratings listed in table 15: absolute maximum ratings , may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality documents. table 15. absolute maximum ratings symbol parameter value unit min max t bias temperature under bias ? 50 125 c t stg storage temperature ? 65 150 c v io (1) input or output voltage 1.8v, v ddq devices ? 0.6 2.7 v 3 v, v ddq devices ? 0.6 4.6 v v dd supply voltage ? 0.6 4.6 v 1. minimum voltage may undershoot to ?2v for less than 20ns during transitions on input and i/o pins. maximum voltage may overshoot to v dd + 2v for less than 20ns duri ng transitions on i/o pins.
nand04ga3c2a, nand04gw3c2a 12 dc and ac parameters 35/51 12 dc and ac parameters this section summarizes the operating and measurement conditions, and the dc and ac characteristics of the device. the parameters in the dc and ac characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in table 16: operating and ac measurement conditions . designers should check that the operating conditions in their circuit match th e measurement conditions when relying on the quoted parameters. the dc and ac characteristics for v ddq 1.8v devices are not yet available. table 16. operating and ac measurement conditions parameter nand04ga3c2a, nand04gw3c2a units min max supply voltage (v dd ) 1.8v, v ddq devices 1.7 1.95 v 3v, v ddq devices 2.7 3.6 v ambient temperature (t a ) grade 1 0 70 c grade 6 ?40 85 c load capacitance (c l ) (1 ttl gate and c l ) 1.8v v ddq devices 30 pf 3v, v ddq devices (2.7 - 3.6v) 50 pf input pulses voltages 1.8v, v ddq devices 0v dd v 3v, v ddq devices 0.4 2.4 v input and output timing ref. voltages 1.8v, v ddq devices 0.9 v 3v, v ddq devices 1.5 v output circuit resistor r ref 8.35 k ? input rise and fall times 5 ns table 17. capacitance (1) symbol parameter test condition typ max unit c in input capacitance v in = 0v 10 pf c i/o input/output capacitance v il = 0v 10 pf 1. t a = 25c, f = 1 mhz. c in and c i/o are not 100% tested.
12 dc and ac parameters nand04ga3c2a, nand04gw3c2a 36/51 table 18. dc characteristics, v ddq 3v devices (1) symbol parameter test conditions min typ max unit i dd1 operating current sequential read t rlrl minimum e =v il, i out = 0 ma -1020ma i dd2 program - - 20 30 ma i dd3 erase - - 15 20 ma i dd4 standby current (ttl) e=v ih , wp =0/v dd 1 ma i dd5 standby current (cmos) e =v dd -0.2, wp =0/v dd - 10 50 a i li input leakage current v in = 0 to 3.6v - - 10 a i lo output leakage current v out = 0 to 3.6v - - 10 a v ih input high voltage - 2.0 - v dd +0.3 v v il input low voltage - -0.3 - 0.8 v v oh output high voltage level i oh = -400a 2.4 - - v v ol output low voltage level i ol = 2.1ma - - 0.4 v i ol (rb ) output low current (rb ) v ol = 0.4v 8 10 ma 1. dc characteristics for v ddq 1.8v devices are still to be determined.
nand04ga3c2a, nand04gw3c2a 12 dc and ac parameters 37/51 table 19. ac characteristics for command, address, data input, v ddq 3v devices (1) symbol alt. symbol parameter 3v i/o unit t allwh t als address latch low to write enable high al setup time min 40 ns t alhwh address latch high to write enable high t clhwh t cls command latch high to write enable high cl setup time min 20 ns t cllwh command latch low to write enable high t dvwh t ds data valid to write enable high data setup time min 20 ns t elwh t cs chip enable low to write enable high e setup time min 30 ns t whalh t alh write enable high to address latch high al hold time min 15 ns t whall write enable high to address latch low t whclh t clh write enable high to command latch high cl hold time min 10 ns t whcll write enable high to command latch low t whdx t dh write enable high to data transition data hold time min 15 ns t wheh t ch write enable high to chip enable high e hold time min 10 ns t whwl t wh write enable high to write enable low w high hold time min 20 ns t wlwh t wp write enable low to write enable high w pulse width min 40 ns t wlwl t wc write enable low to write enable low write cycle time min 60 ns 1. ac characteristics for v ddq 1.8v devices are still to be determined.
12 dc and ac parameters nand04ga3c2a, nand04gw3c2a 38/51 table 20. ac characteristics for operations, v ddq 3v devices (1) symbol alt. symbol parameter 3v i/o unit t allrl1 t ar address latch low to read enable low read electronic signature min 20 ns t allrl2 read cycle min 20 ns t bhrl t rr ready/busy high to read enable low min 20 ns t blbh1 ready/busy low to ready/busy high read busy time max 60 s t blbh2 t prog program busy time max 2000 s t blbh3 t bers erase busy time max 3 ms t blbh4 reset busy time, during ready max 5 s t whbh1 t rst write enable high to ready/busy high reset busy time, during read max 20 s reset busy time, during program max 40 s reset busy time, during erase max 200 s t cllrl t clr command latch low to read enable low min 15 ns t dzrl t ir data hi-z to read enable low min 0 ns t ehqz t chz chip enable high to output hi-z max 30 ns t elqv t cea chip enable low to output valid max 50 ns t rhrl t reh read enable high to read enable low read enable high hold time min 20 ns t rhqz t rhz read enable high to output hi-z max 30 ns t rlrh t rp read enable low to read enable high read enable pulse width min 40 ns t rlrl t rc read enable low to read enable low read cycle time min 60 ns t rlqv t rea read enable low to output valid read enable access time max 45 ns read es access time (2) t whbh t r write enable high to ready/busy high read busy time max 60 s t whbl t wb write enable high to ready/busy low max 100 ns t whrl t whr write enable high to read enable low min 80 ns t vhwh (3) t ww write protection time min 100 ns t vlwh (3) min 100 ns 1. ac characteristics for v ddq 1.8v devices are still to be determined. 2. es = electronic signature. 3. wp high to w high during program/erase enable operations.
nand04ga3c2a, nand04gw3c2a 12 dc and ac parameters 39/51 figure 13. command latch ac waveforms figure 14. address latch ac waveforms ai12705 cl e w al i/o tclhwh telwh twhcll twheh twlwh tallwh twhalh command tdvwh twhdx (cl setup time) (cl hold time) (data setup time) (data hold time) (alsetup time) (al hold time) h(e setup time) (e hold time) ai12706 cl e w al i/o twlwh telwh twlwl tcllwh twhwl talhwh tdvwh twlwl twlwl twlwh twlwh twlwh twhwl twhwl twhdx twhall tdvwh twhdx tdvwh twhdx tdvwh twhdx twhall adrress cycle 1 twhall (al setup time) (al hold time) adrress cycle 4 adrress cycle 3 adrress cycle 2 (cl setup time) (data setup time) (data hold time) (e setup time) adrress cycle 5 twlwl twlwh tdvwh twhdx twhwl twhall
12 dc and ac parameters nand04ga3c2a, nand04gw3c2a 40/51 figure 15. data input latch ac waveforms 1. last data in is 2111b. figure 16. sequential data output after read ac waveforms 1. cl = low, al = low, w = high. twhclh cl e al w i/o tallwh twlwl twlwh twheh twlwh twlwh data in 0 data in 1 data in last tdvwh twhdx tdvwh twhdx tdvwh twhdx ai12707 (data setup time) (data hold time) (alsetup time) (cl hold time) (e hold time) e ai08031 r i/o rb trlrl trlqv trhrl trlqv data out data out data out trhqz tbhrl trlqv trhqz tehqz (read cycle time) (r accesstime) (r high holdtime)
nand04ga3c2a, nand04gw3c2a 12 dc and ac parameters 41/51 figure 17. read status register ac waveform figure 18. read electronic signature ac waveform 1. refer to table 10 for the values of the manufacturer and device codes, and to table 11 and table 12 for the information contained in byte3 and byte 4. telwh tdvwh status register output 70h cl e w r i/o tclhwh twhdx twlwh twhcll tcllrl tdzrl trlqv tehqz trhqz twhrl telqv twheh ai12708 (data setup time) (data hold time) 90h 00h man. code device code cl e w al r i/o trlqv read electronic signature command 1st cycle address ai08667b (read es access time) tallrl1 byte4 byte3 byte1 byte2 see note.1
12 dc and ac parameters nand04ga3c2a, nand04gw3c2a 42/51 figure 19. page read operation ac waveform cl e w al r i/o rb twlwl twhbl tallrl2 00h data n data n+1 data n+2 data last twhbh trlrl tehqz trhqz ai11018b busy command code address n input data output from address n to last byte or word in page add.n cycle 2 add.n cycle 5 add.n cycle 4 add.n cycle 3 (read cycle time) trlrh tblbh1 30h add.n cycle 1
nand04ga3c2a, nand04gw3c2a 12 dc and ac parameters 43/51 figure 20. page program ac waveform cl e w al r i/o rb sr0 ai11019 n last 10h 70h 80h page program setup code confirm code read status register twlwl twlwl twlwl twhbl tblbh2 page program address input data input add.n cycle1 add.n cycle 4 add.n cycle 3 add.n cycle 2 (write cycle time) (program busy time) add.n cycle 5
12 dc and ac parameters nand04ga3c2a, nand04gw3c2a 44/51 figure 21. block erase ac waveform figure 22. reset ac waveform d0h 60h sr0 70h ai08038c twhbl twlwl tblbh3 block erase setup command block erase cl e w al r i/o rb confirm code read status register block address input (erase busy time) (write cycle time) add. cycle 1 add. cycle 3 add. cycle 2 w r i/o rb twhbh1 al cl ffh ai08043b (reset busy time)
nand04ga3c2a, nand04gw3c2a 12 dc and ac parameters 45/51 figure 23. program/erase enable waveform figure 24. program/erase disable waveform w rb tvhwh ai12709 wp i/o 80h 10h w rb tvlwh ai12710 wp i/o 80h 10h high
12 dc and ac parameters nand04ga3c2a, nand04gw3c2a 46/51 12.1 ready/busy signal electrical characteristics figure 25 , figure 26 and figure 27 show the electrical charac teristics for the ready/busy signal. the value required for the resistor r p can be calculated using the following equation: so, where i l is the sum of the input currents of all the devices tied to the ready/busy signal. r p max is determined by the maximum value of t r . figure 25. ready/busy ac waveform figure 26. ready/busy load circuit r p min v ddmax v olmax ? () i ol i l + ------------------------------------------------------------- = r p min 1.8v () 1.85v 3ma i l + --------------------------- = r p min 3v () 3.2v 8ma i l + --------------------------- = ai07564b busy v oh ready v dd v ol t f t r ai07563b r p v dd v ss rb device open drain output ibusy
nand04ga3c2a, nand04gw3c2a 12 dc and ac parameters 47/51 figure 27. resistor value versus waveform timings for ready/busy signal 1. t = 25c. ai11014 r p (k ?) 12 34 100 300 200 t r , t f (ns) 1 2 3 1.7 0.85 30 1.7 1.7 1.7 1.7 t r t f ibusy 0 400 4 r p (k ?) 12 34 100 300 200 1 2 3 ibusy (ma) 2.4 1.2 0.8 0.6 100 200 300 400 3.6 3.6 3.6 3.6 0 400 4 v ddq = 1.8v, c l = 30pf v ddq = 3.3v, c l = 100pf t r , t f (ns) ibusy (ma) 60 90 120 0.57 0.43
13 package mechanical nand04ga3c2a, nand04gw3c2a 48/51 13 package mechanical figure 28. tsop48 - 48 lead plastic thin small outline, 12 x 20 mm, package outline 1. drawing is not to scale. tsop-g b e die c l a1 e1 e a a2 1 24 48 25 d1 l1 cp table 21. tsop48 - 48 lead plastic thin small outline, 12 x 20 mm, package mechanical data symbol millimeters inches typ min max typ min max a 1.200 0.0472 a1 0.100 0.050 0.150 0.0039 0.0020 0.0059 a2 1.000 0.950 1.050 0.0394 0.0374 0.0413 b 0.220 0.170 0.270 0.0087 0.0067 0.0106 c 0.100 0.210 0.0039 0.0083 cp 0.080 0.0031 d1 12.000 11.900 12.100 0.4724 0.4685 0.4764 e 20.000 19.800 20.200 0.7874 0.7795 0.7953 e1 18.400 18.300 18.500 0.7244 0.7205 0.7283 e 0.500 ? ? 0.0197 ? l 0.600 0.500 0.700 0.0236 0.0197 0.0276 l1 0.800 0.0315 a 305305
nand04ga3c2a, nand04gw3c 2a 14 part numbering 49/51 14 part numbering devices are shipped from the factory with the memory content bits, in valid blocks, erased to ?1?. for further information on any aspect of this device, please contact your nearest st sales office. table 22. ordering information scheme example: nand04gw3c2a n 1 e device type nand flash memory density 04g = 4gb operating voltage w = v ddq = 2.7 to 3.6v a = v ddq = 1.7v to 1.95v bus width 3 = x8 family identifier c = 2112 bytes page mlc device options 2 = chip enable don't care enabled product version a = first version package n = tsop48 12 x 20mm (all devices) temperature range 1 = 0 to 70 c 6 = ? 40 to 85 c option e = ecopack package, standard packing f = ecopack package, tape & reel packing
15 revision history nand0 4ga3c2a, nand04gw3c2a 50/51 15 revision history table 23. document revision history date revision changes 16-mar-2006 1 initial release. 09-nov-2006 2 nand08ga2c2a and nand08gw2c2a root part numbers removed.
nand04ga3c2a, nand04gw3c2a 51/51 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 9 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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